Clock multiplier circuit

ABSTRACT

Providing a clock multiplier circuit which generates a multiple clock having a stable frequency from a reference clock without using analog devices  
     The above clock multiplier circuit comprises: a ring oscillator which oscillates at a sufficiently higher frequency than that of the multiple clock; a reference clock counter for counting the sampling output of the reference clock by the output clock of the ring oscillator to obtain the count value of the half cycle of the reference clock; and a multiple clock counter which, in case the value obtained by dividing the count value of the half cycle of the obtained reference clock by the multiplication factor externally given is defined as a multiple count value, inverts the output of the multiple clock output each time it counts the multiple count value by the output clock of the ring oscillator.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a clock multiplier circuit for generating a clock whose frequency is a multiple of a reference clock.

[0003] 2. Description of the Related Art

[0004] In the related art, a PLL (Phase-locked Loop) incorporating a VCO (Voltage-controlled Oscillator) has been used to obtain a clock signal whose frequency is a multiple of a reference clock. FIG. 5 is a block diagram showing the configuration of such a conventional clock multiplier circuit using PLL.

[0005] In FIG. 5, a numeral 501 represents a reference clock, 502 a multiple clock output, 511 a phase comparator, 512 a charge pump, 513 a low pass filter, 514 a VCO, 515 a frequency divider, and 516 a waveform shaping circuit.

[0006] The reference clock 501 input to the phase comparator 511 is compared with the output of the frequency divider which divides the output of the VCO 514 by N. A control voltage generated by the charge pump 512 and the low pass filter 513 from the phase difference output is supplied to the VCO 514. The control voltage controls the VCO 514 set to oscillate a frequency N times the reference clock 510 for loop control by the PLL. The waveform shaping circuit 516 performs waveform shaping so that the duty cycle of the output waveform of the VCO 514 will be ½.

[0007] However, the conventional clock multiplier circuit has two major problems. The first problem is that the low pass filter requires a large time constant in order to stabilize a desired multiple frequency in the conventional clock multiplier circuit. When the low pass filter is built into an LSI, a greater value of a resistor or capacitor as analog devices is required. Due to an increase in the chip size caused by an increase in the footprint of the analog devices or variation in the resistors or capacitors, the PLL could oscillate a signal without locking the phase.

[0008] The second problem is that a lock-up time is required to obtain a stable oscillating frequency. FIG. 6 shows the transition in the output frequency of a conventional clock multiplier circuit using a PLL at the start of operation of the output frequency. As shown in FIG. 6, a clock multiplier circuit using a conventional PLL is accompanied by waste of operation time and current consumption before a stable oscillating frequency is obtained.

SUMMARY OF THE INVENTION

[0009] The invention has been proposed in view of the aforementioned circumstances and aims at providing a clock multiplier circuit for generating a clock obtained by multiplying the frequency of a reference clock without using analog devices required by a PLL, in order to obtain a stable frequency.

[0010] In order to solve the problems, a clock multiplier circuit according to a first aspect of the invention is a clock multiplier circuit which outputs a multiple clock having a frequency of a multiplication factor externally given with regard to a reference clock, characterized by comprising: a ring oscillator which oscillates at a sufficiently higher frequency than that of the multiple clock; a reference clock counter for counting the sampling output of the reference clock by the output clock of the ring oscillator to obtain the count value of the half cycle of the reference clock; and a multiple clock counter which, in case the value obtained by dividing the count value of the half cycle of the obtained reference clock by the multiplication factor is defined as a multiple count value, inverts the output of the multiple clock output each time it counts the multiple count value by the output clock of the ring oscillator.

[0011] With this configuration, by eliminating analog devices and generating a multiple clock in a circuit which counts a multiple count value, a clock multiplier circuit without a feedback loop is provided, thereby obtaining an output free from a transient response observed in a PLL.

[0012] A multiple clock is generated by obtaining the count value of the half cycle of the reference clock from the output clock of a free-run ring oscillator, and counting the multiple count value from the output clock of the free-run ring oscillator. Thus, even in case the. oscillating frequency of the ring oscillator varies due to a variation in the source voltage or temperature, correction according to the variation is automatically performed.

[0013] A clock multiplier circuit according to a second aspect of the invention is a clock multiplier circuit according to the first aspect, characterized in that the ring oscillator comprises an odd number of inverter stages.

[0014] With this configuration, the ring oscillator comprises an odd number of stages so that it is not necessary to use the oscillating frequency control voltage range (dynamic range) required in case a VCO issued. This readily reduces the voltage of the circuit.

[0015] A clock multiplier circuit according to a third aspect of the invention is a clock multiplier circuit according to the first or second aspect, characterized in that the multiple clock counter starts counting of a multiple count value in synchronization with the inversion per half cycle of the reference clock.

[0016] With this configuration, counting to generate a multiple clock is started in synchronization with the inversion per half cycle of the reference clock. Thus it is possible to align the phase of the multiple clock with that of the reference clock without using a phase comparator.

[0017] A clock multiplier circuit according to a fourth aspect of the invention is a clock multiplier circuit according any one of the first through third aspects, the clock multiplier circuit further comprising an unlock detection circuit, characterized in that the multiple clock counter generates a count end pulse each time it counts the multiple count value and that the unlock detection circuit determines detection of an unlock in case the count end pulse is not detected within a cycle of the reference clock and restarts the ring oscillator based on determination of the detection of unlock.

[0018] With this configuration, by determining detection of an unlock in case a count end pulse is not detected within a cycle of the reference clock, it is possible to detect a case where a multiple clock is not obtained because the ring oscillator is shut down. By restarting the ring oscillator based on the determination of detection of an unlock, it is possible to automatically reset the operation of the clock multiplier circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019]FIG. 1 is a block diagram showing a configuration of a clock multiplier circuit according to an embodiment of the invention;

[0020]FIG. 2 is a circuit diagram showing an example of configuration of a ring oscillator to which an odd number of inverter stages are connected;

[0021]FIG. 3 is a timing chart illustrating the operation of the ring oscillator to which an odd number of inverter stages are connected;

[0022]FIG. 4 is a timing chart illustrating the operation of the clock multiplier circuit according to an embodiment of the invention;

[0023]FIG. 5 is a block diagram showing the configuration of a related art clock multiplier circuit using a PLL; and

[0024]FIG. 6 shows the transition in the output frequency of a related art clock multiplier circuit using a PLL at the start of operation of the output frequency.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0025] An embodiment of the invention will be described referring to the drawings.

[0026]FIG. 1 is a block diagram showing a configuration of a clock multiplier circuit according to an embodiment of the invention. In FIG. 1, a numeral 101 represents a reference clock, 102 a multiple clock output, 103 a multiplication factor input, 104 an unlock detection output, 111 a ring oscillator, 112 a reference clock counter, 113 a multiplication factor setting circuit, 114 a multiple clock counter, 115 an unlock detection circuit, and 116 a resetting circuit.

[0027] The ring oscillator 111 is a circuit oscillating a clock having a frequency sufficiently higher than a reference clock and a multiple clock. The ring oscillator 111 does not require a high accuracy so that it is implemented easily by connecting an odd number of inverter stages. FIG. 2 is a circuit diagram showing an example of configuration of a ring oscillator to which an odd number of inverter stages are connected. In FIG. 2, a numeral 201 represents a reset signal, 202 a reset pulse S4, 211 and 212 through 215 inverter stages, 216 a start pulse application circuit and 217 an OR circuit.

[0028]FIG. 3 is a timing chart illustrating the operation of the ring oscillator 111 shown in FIG. 2. As shown in FIG. 3, the output of the inverter 211 is fixed to low so that the operation of the ring oscillator is halted while the reset signal is being input.

[0029] When the reset signal 201 is driven Low, the ring oscillator 111 starts its operation at an oscillating frequency determined by the delay time of an odd number of inverter stages. In the event of a halt of oscillation assumed in case the input/output of the odd number of inverter stages has reached an intermediate potential, the return pulse S4 is applied to the start pulse application circuit 216 via the OR circuit 218 to restart the ring oscillator 111.

[0030]FIG. 4 is a timing chart illustrating the operation of the clock multiplier circuit of the above configuration. Operation of the clock multiplier circuit of the invention will be described referring to FIGS., 1 through 4. For ease of description, it is assumed that the oscillating frequency f1 of the ring oscillator 111 is about 20 MHz, the frequency f0 of the reference clock 101 as 1 MHz, the frequency f2 of the multiple clock 102 is 2 MHz, that is, the multiplication factor N equals 2.

[0031] In the reference clock counter 112, the reference clock 101 is sampled by using the output clock f1 of the ring oscillator 111 and the sampling pulses up to inversion of the reference clock 101 are counted to obtain the sampling value M of a half cycle of the reference clock 101 which equals 10.

[0032] In the sampling operation, the variation point of the reference clock 101 is seized in synchronization of the output clock of the ring oscillator 111 in order to avoid a hazard. For example, the variation point of the reference clock 101 is seized on the trailing edge of the output clock of the ring oscillator 111 and the reference clock counter 112 is operated on the leading edge thereof.

[0033] The multiplication factor setting circuit 113 calculates the multiple count value M/N=5 from the sampling value M of a half cycle of the reference clock 101 which equals 10 and the multiplication factor N=2 given by an input of multiplication factor. The latest value of the multiple count value M/N is input to the multiple clock counter 114 at any time.

[0034] The multiple clock counter 114 samples the reference clock 101 with the output clock f1 of the ring oscillator 111 to seize the variation point where the reference clock 101 is inverted, and counts the output clock f1 starting from the variation point and inverting the output each time the count reaches the multiple count value M/N, thereby generating the multiple clock 102 having a half cycle 1/N times that of the reference clock, that is, a frequency f2 N times the frequency f1 of the reference clock.

[0035] In the sampling operation, same as the case of the reference clock counter 112, the variation point of the reference clock 101 is seized in synchronization of the output clock of the ring oscillator 111 in order to avoid a hazard. For example, the variation point of the reference clock 101 is seized on the trailing edge of the output clock of the ring oscillator 111 and the multiple clock counter 114 is operated on the leading edge thereof.

[0036] A pulse S1 output in each cycle of the reference clock 101 is supplied to the unlock detection circuit 115. From the multiple clock counter 114, a count end pulse S2 indicating that counting is complete up to the multiple count value M/N is supplied to the unlock detection circuit 115. In case the count end pulse is not generated per reference clock, this phenomenon is detected as an unlock.

[0037] The unlock detection circuit 115 comprises, for example, a flip-flop set with the pulse S1 and reset with the count end pulse S2. In case the flip-flop is set when the pulse is input, this phenomenon is readily detected as an unlock.

[0038] The resetting circuit 116, in response to a variation in the output of the unlock detection circuit 115, generates a reset pulse S4 and applies the reset pulse. S4 to the ring oscillator 111 in order to restart the ring oscillator 111. Resetting of the clock multiplier circuit is enabled in case the unlock is caused by shutdown of the ring oscillator.

[0039] In the above operation, the reference clock counter 112 uses the output clock of the ring oscillator 111 to seize the variation point of the reference clock 101 to acquire the half-cycle sampling value M. The multiple clock counter 114 uses the same output clock of the ring oscillator 111 to count up to the multiple count value M/N. Even in case the oscillating frequency of the ring oscillator 111 varies, correction according to the variation is automatically performed.

[0040] This operation will be described referring to FIG. 4. At time t1, the sampling value M=10 is obtained. The multiple count value M/N=5 is calculated. The multiple clock 102 (f2) is inverted per five pulses of the output clock f1 of the ring oscillator. At time t2, the oscillating frequency f1 of the ring oscillator 111 varies and the sampling value M=7 is obtained. Thus the multiple count value M/N=3 is calculated. The multiple clock 102 (f2) is inverted per three pulses of the output clock f1 of the ring oscillator. The last half cycle shows a waveform containing a phase error.

[0041] The multiple clock counter 114 counts the output clock f1 of the ring oscillator, starting from the variation point of the reference clock 101 so as to align the phase of the generated multiple clock 102 with that of the reference clock 101. This approach is not a direct phase synchronization, so that accuracy per multiple clock pulse is lower than that of a PLL. However, it is possible to align the time per reference clock cycle and readily generate a phase-synchronized N-fold multiple clock.

[0042] As mentioned hereabove, according to the invention, by generating a multiple clock in a circuit which counts a multiple count value, analog devices in the circuit are eliminated. This scales down an LSI chip in the circuit and provides a clock multiple circuit without a feedback loop, thereby obtaining an output free from a transient response observed in a PLL.

[0043] According to the invention, the count value of a half cycle of the reference clock is obtained by using the output clock of a free-run ring oscillator. A multiple clock is generated by counting a multiple count value through use of the same output clock of the ring oscillator. Thus, even in case the oscillating frequency of the ring oscillator varies due to a variation in the source voltage or temperature, correction according to the variation is automatically performed.

[0044] According to the invention, the ring oscillator comprises an off number of inverter stages. The resulting circuit design is easier than a circuit using analog devices so that it is not necessary to use the oscillating frequency control voltage range (dynamic range) required in case a VCO is used. This readily reduces the voltage of the circuit.

[0045] According to the invention, counting to generate a multiple clock is started in synchronization with the inversion per half cycle of the reference clock. Thus it is possible to align the phase of the multiple clock with that of the reference clock without using a phase comparator.

[0046] According to the invention, by determining detection of an unlock in case a count end pulse is not detected within a cycle of the reference clock, it is possible to detect a case where a multiple clock is not obtained because the ring oscillator is shut down. By restarting the ring oscillator based on the determination of detection of an unlock, it is possible to automatically reset the operation of the clock multiplier circuit. 

What is claimed is:
 1. A clock multiplier circuit which outputs a multiple clock having a frequency of a multiplication factor externally given with regard to a reference clock, comprising: a ring oscillator which oscillates at a sufficiently higher frequency than that of said multiple clock; a reference clock counter for counting the sampling output of the reference clock by the output clock of the ring oscillator to obtain the count value of the half cycle of the reference clock; and a multiple clock counter which, in case the value obtained by dividing the count value of the half cycle of said reference clock by said multiplication factor is defined as a multiple count value, inverts the output of said multiple clock output each time it counts said multiple count value by the output clock of said ring oscillator.
 2. A clock multiplier circuit according to claim 1, wherein said ring oscillator comprises an odd number of inverter stages.
 3. A clock multiplier circuit according to claim 1 or 2, wherein said multiple clock counter starts counting of a multiple count value in synchronization with the inversion per half cycle of said reference clock.
 4. A clock multiplier circuit according any one of claims through 3, further comprising: an unlock detection circuit; wherein said multiple clock counter generates a count and pulse each time it counts said multiple count value and that said unlock detection circuit determines detection of an unlock in case said count end pulse is not detected within a cycle of said reference clock and restarts said ring oscillator based on determination of said detection of unlock. 